The present invention is directed to the formation of source/drain regions in integrated circuits, particular to the formation of such regions using pulsed laser doping, and more particularly to a doping sequence for forming ultra shallow source/drain junctions through a silicide contact layer using patterned pulsed laser energy.
As lateral dimensions shrink in metal oxide semiconductor (MOS) integrated circuit (IC) technology, it has become increasingly more difficult to fabricate source/drain regions with acceptable electrical characteristics at high yields. Specifically, the source/drain junctions must have very shallow vertical depth (&lt;100 nm), very low sheet and contact resistance, and low reverse bias leakage currents.
Several technologies for shallow junction formation are actively being investigated. These include low energy ion implantation, plasma immersion ion implantation, and rapid thermal diffusion, either from a solid source or the vapor phase. Each of these technologies has its limitations. All require photo-resist masking and high temperature anneals. Implant processes induce damage in the semiconductor crystal and present difficulties when sub-100-nm p-type junctions are desired; whereas rapid thermal diffusions require complex masking layers and very tight control of the wafer temperature and diffusion times. As a result, these technologies make IC processing more complex, the antithesis to the inductries desired goals of process simplification.
Recently excimer laser annealing for MOS devices of less than a quarter micron has been investigated, wherein an excimer laser having a wavelength of 308 nm was utilized to form shallow junctions of depths less than 100 nm. See H. Tsukamoto et al, Selective Annealing Utilizing Single Pulse Excimer Laser Irradiation for Short Channel Metal Oxide Semiconductor Field Effect Transistors, Jpn.J Appli Phys., Vol. 32, pp L967-970, Part 2, No. 713, 15 Jul. 1993.
Also, an alternative deep-submicrometer doping technology is being developed, known as Projection Gas Immersion Laser Doping (P-GILD), which is a more attractive solution to advanced MOS source/drain fabrication, and involves a marriage of lithography and diffusion. P-GILD is a resistless, step-and-repeat doping process that utilizes excimer laser light patterned by a dielectric recticle to selectively heat and, thereby, dope regions of an integrated circuit. See K. H. Weiner et al, Fabrication of Sub-40-nm p-n Junctions for 0.18 .mu.m MOS Device Applications Using a Cluster-Tool-Compatible, Nanosecond Thermal Doping Technique, September 1993. This excimer laser based process eliminates the need for photoresist masking during the doping sequence, saving many steps. Junctions formed by this process are also ideal for deep-submicrometer (&lt;0.1 .mu.m) transistor operation. However, the standard P-GILD process relies on melting of the silicon in the source/drain region to both incorporate and diffuse the impurity or dopant atoms. The melting process may introduce special problems that make the technique hard to integrate seamlessly into standard production technologies. First, when melting the source drain region, it may be difficult not to melt the gate which can result in catastrophic failure of the device. Also, a typical MOS device structure incorporates many thin dielectric films which interfere, optically, with the laser irradiation. If the interference is constructive, a significant amount of energy can be coupled into regions of the device where no energy is actually desired. Again, catastrophic failure of the device can occur. Finally, topology in the region of the melting silicon will tend to self-planarize, again inducing poor device performance. Each of these problems can be addressed, but this requires specific changes in device structure that are not directly related to the doping process. Such changes are difficult to justify economically and also with respect to technology risk.
Thus, it is seen that there is a need in that art to enable the formation of ultrashallow source/drain junctions and which reduces the cost and complexity of forming source/drain regions in MOS integrated circuits. The present invention provides a solution to the above-referenced problems, constitutes a variation of the P-GILD approach, and can be effectively utilized to fabricate source/drain junctions equivalent or superior in performance to alternative technique or superior in performance to alternative techniques with a process and equipment that is much less complex than that used for the or P-GILD or other, more conventional technologies. The fabrication approach of this invention can be integrated seemlessly into standard production processes. No melting processes are used so no changes are required in device structure.